1. Technical Field
The present disclosure relates to memory devices, and, more particularly, to a semiconductor memory device having a latency controller providing a power-saving effect.
2. Discussion of Related Art
In general, semiconductor memory devices receive an external clock signal and generate at least one clock signal required for their internal operation in response to the external clock signal. A typical synchronous semiconductor memory device provides a latency (i.e., the time it takes to access a particular location in storage) function. A system having the semiconductor memory device may easily use the semiconductor memory device due to the latency function because the semiconductor memory device designates a latency value corresponding to the number of clocks after an external command is applied and before effective data is output.
Thus, when a read command is applied, a semiconductor memory device having a latency function externally outputs data after the number of clocks corresponding to a set latency. However, since the internal clock signal of the semiconductor memory device differs from the external clock signal thereof, the semiconductor memory device needs a latency controller that effectively controls the output timing of data to output the data in synchronization with the external clock signal and that can save power without causing malfunctions when a precharge or power-down command is applied after application of the read command.